MT41K128M8DA-107:J is a DDR3L SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
- 128Meg x 8 configuration, data rate is 1866MT/s
- Packaging style is 78-ball 8mm x 10.5mm FBGA
- Timing (cycle time) is 1.07ns at CL = 13 (DDR3-1866)
- Operating temperature range is 0°C to +95°C, multipurpose register
- Supply voltage range is 1.283V to 1.45V, output driver calibration
- Differential bidirectional data strobe, 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#), 8 internal banks
- Programmable CAS (READ) latency (CL), programmable CAS additive latency (AL)
- Selectable BC4 or BL8 on-the-fly (OTF), self refresh mode
- Self refresh temperature (SRT), automatic self refresh (ASR)
Other details
| Brand |
MICRON |
| Part Number |
MT41K128M8DA-107J |
| Quantity |
Each |
| Technical Data Sheet EN |
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